Current Issue : April - June Volume : 2012 Issue Number : 2 Articles : 4 Articles
This paper presents a framework for high-level power estimation of multiprocessor systems-on-chip (MPSoC) architectures on\nFPGA. The technique is based on abstract execution profiles, called event signatures, and it operates at a higher level of abstraction\nthan, for example, commonly used instruction-set simulator (ISS)-based power estimation methods and should thus be capable\nof achieving good evaluation performance. As a consequence, the technique can be very useful in the context of early systemlevel\ndesign space exploration. We integrated the power estimation technique in a system-level MPSoC synthesis framework.\nSubsequently, using this framework, we designed a range of different candidate architectures which contain different numbers of\nMicroBlaze processors and compared our power estimation results to those from real measurements on a Virtex-6 FPGA board....
System adaptivity is becoming an important feature of modern embedded multiprocessor systems. To achieve the goal of system\r\nadaptivity when executing Polyhedral Process Networks (PPNs) on a generic tiled Network-on-Chip (NoC) MPSoC platform, we\r\npropose an approach to enable the run-time migration of processes among the available platform resources. In our approach,\r\nprocess migration is allowed by a middleware layer which comprises two main components. The first component concerns the\r\ninter-tile data communication between processes. We develop and evaluate a number of different communication approaches\r\nwhich implement the semantics of the PPN model of computation on a generic NoC platform. The presented communication\r\napproaches do not depend on the mapping of processes and have been implemented on a Network-on-Chip multiprocessor\r\nplatform prototyped on an FPGA. Their comparison in terms of the introduced overhead is presented in two case studies\r\nwith different communication characteristics. The second middleware component allows the actual run-time migration of PPN\r\nprocesses. To this end, we propose and evaluate a process migration mechanism which leverages the PPN model of computation to\r\nguarantee a predictable and efficient migration procedure. The efficiency and applicability of the proposed migration mechanism\r\nis shown in a real-life case study....
Scatter Search is an effective and established population-based metaheuristic that has been used to solve a variety of hard\noptimization problems. However, the time required to find high-quality solutions can become prohibitive as problem sizes grow.\nIn this paper, we present a hardware implementation of Scatter Search on a field-programmable gate array (FPGA). Our objective\nis to improve the run time of Scatter Search by exploiting the potentially massive performance benefits that are available through\nthe native parallelism in hardware. When implementing Scatter Search we employ two different high-level languages (HLLs):\nHandel-C and Impulse-C. Our empirical results show that by effectively exploiting source-code optimizations, data parallelism,\nand pipelining, a 28x speed up over software can be achieved....
We present a lossless and low-complexity image compression algorithm for endoscopic images. The algorithm consists of a static\nprediction scheme and a combination of golomb-rice and unary encoding. It does not require any buffer memory and is suitable\nto work with any commercial low-power image sensors that output image pixels in raster-scan fashion. The proposed lossless\nalgorithm has compression ratio of approximately 73% for endoscopic images. Compared to the existing lossless compression\nstandard such as JPEG-LS, the proposed scheme has better compression ratio, lower computational complexity, and lessermemory\nrequirement. The algorithm is implemented in a 0.18 Ã?µm CMOS technology and consumes 0.16mm Ã?â?? 0.16mm silicon area and\n18 Ã?µWof power when working at 2 frames per second....
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